Dynamic Random Access Memory (DRAM) is utilized in modern computing architectures. DRAM may provide advantages of structural simplicity, low cost and speed in comparison to alternative types of memory.
Presently, DRAM commonly utilizes memory cells having one capacitor in combination with a transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. One of the limitations to scalability of present 1T-1C configurations is that it is proving difficult to incorporate capacitors having sufficiently high capacitance into highly-integrated architectures. Accordingly, it would be desirable to develop new memory cell configurations suitable for incorporation into highly-integrated modern memory architectures, and to develop memory array architectures suitable for utilizing such new memory cell configurations.